A Comparative Analysis of Low Power Schmitt Trigger Circuits in Advanced Semiconductor Technologies

Abstract

This paper presents an extensive investigation into Schmitt trigger circuit design, with a focus on developing a Voltage Bootstrapped Schmitt Trigger (VB-ST) circuit optimized for efficiency and noise immunity. The analysis encompasses critical parameters like power consumption, leakage power, and propagation delay under various operating conditions, including different temperatures. Across semiconductor technology models spanning 90nm CMOS, BSIM4, and advanced 7nm FINFET technologies, both self-bias and non-self-bias configurations are examined. The results highlight the clear advantages of the self-biased VB-ST design, consistently outperforming its non-self-biased counterpart. It achieves lower average power consumption and leakage power while demonstrating faster propagation delays, making it an ideal choice for applications requiring rapid response times. The use of NMOS transistors for voltage bootstrapping minimizes negative bias temperature instability (NBTI) effects, enhancing its aging resilience. The incorporation of voltage bootstrapping and a feedback loop further enhances noise immunity and extends voltage swing capabilities. Consequently, the self-biased VB-ST circuit proves highly suitable for applications such as signal conditioning, noise filtering, waveform shaping, analog-to-digital conversion, and power management in electronic systems, particularly in advanced semiconductor technologies.