Energy-Efficient SAR-ADC Architecture for 6G - Applications

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Shalini P , Uma Maheshwari T , Venkateshappa

Abstract

As high-speed wireless communication and sensing technologies advance in the D-band (110–170 GHz), there is an increasing demand for efficient, low-power digital-to-analog (DAC) and analog-to-digital converters (ADC). This paper introduces an innovative multiplexed R-2R DAC paired with a successive approximation register (SAR) ADC, designed specifically to optimize performance in high-frequency D-band applications. The proposed architecture leverages the efficiency of the R-2R ladder to achieve low-power operation while ensuring high linearity. Additionally, multiplexing enhances throughput without significantly increasing power consumption. The SAR ADC is optimized for energy-efficient high-speed conversion, making it suitable for power-constrained mm Wave systems. The design is implemented in a 180nmCMOS-based technology process in cadence design suite and demonstrates superior power efficiency, compact area utilization, and high signal integrity, making it a viable solution for next-generation high-frequency applications such as 6G communication, radar, and high-resolution imaging.

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