Design And Analysis Of Energy Efficient Current Starved VCO With Sleep Stack Approach For PLL Applications

Abstract

This study compares the performance of the Current Starved Voltage Controlled Oscillator (CSVCO) for Phase Locked Loop (PLL) solutions. To complete the current job, or the design of the Current Starved VCO, the sleep stack reduced power leakage technique is used.With a 0.45V supply voltage and 45nm CMOS technology, it has been implemented using Cadence Software. Characteristics including latency, oscillation frequency, and average power are calculated. The improved cadence simulation performance results are recorded. The proposed PLL implementation parameters with Sleep Stack are confirmed to be significantly smaller on a chip than earlier approaches.while using a lot less electricity and far more efficiency. This is verified by contrasting the different PLL implementation parameters using Basic CSVCO and Sleep Stack CSVCO. For low-power applications, the sleep stack method works best. The proposed PLL architecture employing the Sleep Stack Technique successfully lowers sub-threshold leakage current. A frequency of 2.759 GHz, power of 2.559 µw, phase noise of -63.8 (dBc/Hz), and latency (µs) of 0.0006544 are also attained.