VLSI design of a Novel Encryption Standard using Nano Technology
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Abstract
Due to the increasing number of small internet-connected devices, end-to-end security is of the utmost importance in the World Wide Web of Things (IoT). Encryption must be tailored to work with Internet of Things products because they aren't exactly flush with cash. According to this scholarly research, resource-constrained Internet of Things (IoT) devices may benefit from using the newest version of encryption (AES) with a field-programmable gated arrays (FPGA) using 65-nm technology. You may think of the proposed 8-bit data path as having five major components. All of this transitional data, plaintext, as well as keys are stored in two separate registry banks: the Key-Register and the State-Register. The incorporation of Shift-Rows into the State Register allows for more efficient use of space. We built an 8-bit efficient block with four internal registers that read in 8 bits while sending them out; this allowed us to transform the Mix-Column to an 8-bit data channel. In addition, both the password expansion as well as encryption processes share an optimized Sub-Byte. Some Sub-Bytes were consolidated and streamlined in order to increase performance. The clock gating technique is included in the design to reduce power consumption. There was a 35% to 2.4% improvement in application-specific integrated circuit (ASIC) performance when compared to earlier research of a same nature. Based on the findings, it appears that the proposed design is an excellent cryptosystem for IoT devices with limited power consumption.
The following terms are used in the index: lightweight cryptography, Internet of Things (IoT), clock gating, and Advanced Encryption Standard, also algorithm.