Efficient Fault Coverage Automatic Test Pattern Generation Using Genetic Algorithm for Combinational Systems

Abstract

A crucial step in the design of every digital integrated circuit is testing. It's critical to identify and diagnose the issues with an IC. A test vector is a set of inputs provided to the IC to test it. Generally, programs called test vector generation create test data automatically for automated testing circuits. Numerous distinct test vectors may result from this. For simpler designs, manual testing can be carried out by forcing values into the system and then watching the results. Automation is necessary because testing becomes tiresome as design complexity rises. Smaller designs can undergo manual testing, where inputs are provided to the system by forcing values and monitoring the results. Automating testing becomes necessary as design complexity rises since it becomes tiresome. The Automated Test Pattern Generator (ATPG) is required for VLSI testing to obtain input test vectors for the Device Under Test (DUT). In this paper we present a new way to generate ATPG vectors using probability weights and find the optimal set of vector for the weights using genetic algorithm (GA) on excess three encoder as our DUT. The excess three encoder was simulated for stuck at fault modelling. We find that our approach has yielded promising results compared to other ATPG algorithms.