Design of Area Efficient Vedic Multiplier using Parallel Prefix Adder

Abstract

The fundamental incentive of this paper is to give the design and implementation of Area Efficient 16x16 Vedic Multiplier. Vedic mathematics is a mathematical system, rooted in ancient Indian techniques that simplifies mathematical operations, enabling quicker and easier problem-solving.  The goal here is to implement a Vedic multiplier based on the Urdhva Tiryagbhyam Sutra to maximize the speed of multiplication by using Parallel Prefix Adder (PPA) - Ladner-Fischer adder. Parallel prefix adder (PPA) is one among the fast adders which can be used in data path applications to minimize the overall delay involved in addition. The integration of these algorithms produces a novel multiplier design that optimizes speed while minimizing area and power consumption. This design meets the demands of modern high-speed computing and digital signal processing applications. The performance metrics of the proposed Vedic multiplier are evaluated and compared with those of existing Vedic multipliers and traditional multipliers. The algorithm was implemented and verified using Verilog HDL in Xilinx 14.7 and Cadence tools to ensure the accuracy of the results