High Speed Compressor Design Using Reversible Logic for Approximate Computing

Abstract

The Dual stage 4:2 compressor proposed in this study has a new architecture and an inexact Baugh-Wooley Wallace tree multiplier with reversible logic optimization for realization. The suggested Dual stage 4:2 compressor and Baugh-Wooley Wallace tree multiplier's effectiveness is evaluated using the scales of Gate Count (GC), Quantum Cost (QC), Garbage Output (GO), and Ancilla Input (AI). This paper implements an 8 8 Baugh-Wooley Wallace tree multiplier. The proposed multiplier is evaluated using the accuracy metrics MED and MRED, and it is discovered to be the least accurate among existing imprecise compressor-based multiplier designs. There are two uses for the suggested multiplier. Convolutional Neural Networks (CNN) and one-level decomposition of images using a rationalized db6 wavelet filter bank are two examples of image processing.