High Speed Ternary Content Addressable Memory for Network Applications Using Transmission Gate Logic

Abstract

Ternary Content Addressable Memory (TCAM) is a critical component in modern network systems, widely used for high-speed packet transmission and classification tasks in routing tables because of its superior lookup speed. However, the substantial number of transistors used for its operation results in noteworthy power utilization and delay. This paper explore traditional TCAM designs alongside advancements aimed at improving performance, reducing power utilization, and improving searching speed. Leveraging power gating and Transmission Gate Logic (TGL), the proposed TCAM architecture enhances energy efficiency while ensuring data security. The proposed architecture aims at reducing dynamic along with leakage power. The work is carried out in cadence virtuoso 45nm and the result has shown that there is significant reduction in delay and bearable power consumption. The delay is observed to be 56.7ps and the overall power consumption of 92.91uW. The results when compared with the architecture used in previous work shows significant improvement in delay that is, up to 84%, with a sustainable increase in power utilization to about 13%.