Power-Optimized Approximate Multiplier with Tunable Accuracy

Abstract

Multiplication plays a crucial role in signal processing algorithms. However, designing efficient multipliers poses inherent challenges, including substantial area requirements, extended latency, and significant power consumption. Attention now turns to designing compressors with the goal of reducing power consumption, latency, and the number of steps involved in the product computation process in order to address these problems. In particular, this paper presents a novel strategy by suggesting a roughly optimized compressor design that is deliberately used to reduce the multiplier's stage count. Specifically, the paper introduces an innovative approach through the proposition of an approximate compressor design, strategically employed to decrease the number of stages in a multiplier. The presented multiplier architecture utilizes dynamic input truncation, in which lower significance bits of the input operands are removed in each multiplication operation depending on the acceptable level of accuracy loss for the target application. The emphasis on approximation allows for a reduction in computational complexity, providing a potential solution to the challenges posed by traditional multiplier designs. This proposed work is designed and analyzed using the Xilinx Vivado tool.