High Performance and Area Efficient Approximate LUT Based Adder for Realtime Applications

Abstract

In this project, high speed, power efficient adder was designed at the cost of accuracy. The proposed design fixes the LSP of the implementation which will truncate half of the adder area and there by reduces the power consumption along with that the propagation delay can be minimized to half of it and further can be optimized by inner stage input-output pipelining to the adder to increase its speed. The MSP utilizes the accurate computation utilizes LUT's as resources and reduces the parameters by slightly increasing the error of approximate adders. Compared to the existing LEADx and APEx now our suggested adder is efficient in parameters and the design and simulation and effectiveness of the proposed method is synthesized using Xilinx Vivado.